FIG. 1 is an illustration of a conventional four transistor (4T) imaging pixel 100. The imaging pixel 100 includes a light sensitive element 101, shown as a photodiode, a floating diffusion node C, and four transistors: a transfer transistor 111, a reset transistor 112, a first source follower transistor 113, and a row select transistor 114. The imaging pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 111, a RST control signal for controlling the conductivity of the reset transistor 112, and a ROW control signal for controlling the conductivity of the row select transistor 114. The voltage at the floating diffusion node C controls the conductivity of the first source follower transistor 113. The output of the source follow transistor is presented to the load circuit 120 through the row select transistor 114, which outputs a pixel signal at node B, when the row select transistor 114 is conducting. The output at node B may be routed to column circuitry 220 (FIG. 2) of an imager 200, as discussed in greater detail below.
The states of the transfer and reset transistors 111, 112 are used to determine whether the floating diffusion node C is coupled to the light sensitive element 101 for receiving a photo generated charge as generated by the light sensitive element 101 during a charge integration period or a source of pixel power VAAPIX at node A during a reset period.
The imaging pixel 100 is operated as follows. The ROW control signal is asserted to cause the row select transistor 114 to conduct. At the same time, the RST control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion node C to the pixel power VAAPIX at node A, and resets the voltage at node C to the pixel power VAAPIX. The imaging pixel 100 outputs a reset signal Vrst at node B.
After the reset signal Vrst has been output, the RST control signal is deasserted. The light sensitive element 101 is exposed to incident light and accumulates charges based on the level of the incident light during a charge integration period. After the charge integration period, the TX control signal is asserted. This couples the floating diffusion node C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion node C. The imaging pixel 100 outputs a photo signal Vsig at node B. The reset and photo signals Vrst, Vsig are different components of the overall pixel output (i.e., Voutput=Vrst−Vsig).
FIGS. 2A and 2B are illustrations of an imager 200. The imager 200 includes a pixel array 201 comprising a plurality of imaging pixels 100 organized into rows and columns in an imaging portion 201b of the pixel array 201. The pixel array 201 may also include a non-imaging portion 201a, which comprises a plurality of non-imaging pixels 100′, for example, barrier pixels or dark pixels. Non-imaging pixels 100′ are similar to imaging pixels, but do not produce outputs which are further processed by the imager 200.
The imager 200 also includes row circuitry 210, column circuitry 220, an analog-to-digital converter 230, a digital processing circuit 240, and a storage device 250. The imager 200 also includes a controller 260. The row circuitry 210 selects a row of pixels 100 from the pixel array 201. The imaging pixels 100 in the selected row output their reset and pixel signals Vrst, Vsig to the column circuitry 220, which samples and holds the reset and pixel signals Vrst, Vsig. The column circuitry 220 also forms the pixel output (Vrst−Vsig), which is presented to the analog-to-digital converter 230 that converts the difference signal to a digital value. The digital value is then processed by the digital processing circuit 240, which stores the processed value in the storage device 250 for output. The controller 260 is coupled to the pixel array 201, row circuitry 210, column circuitry 220, digital processing circuit 240, and storage device 250, and provides control signals to perform the above described processing.
As shown in FIG. 2B, the column circuitry 220 may employ a column parallel analog to digital architecture, which includes a plurality of column circuits 221 for receiving, in parallel, a plurality of reset and photo signals Vrst, Vsig from a plurality of imaging pixels 100 in a selected row. Each column circuit 221 samples and holds the reset and photo signals Vrst, Vsig as they are received and converts each sampled signal Vrst, Vsig into a digital code proportional to the difference between signals Vrst and Vsig. The digital code is typically stored in a column memory, which can be sequentially selected to preset the stored digital code to digital processing 240. The analog to digital converters can be any type of converter, including, for example, SAR, single slope, dual slope, cyclic 1.5 bit, or other types of converters. Although the non-imaging pixels 100′ of the selected row do not produce signals that are subsequently processed by the imager 200, typically the column circuitry includes column circuits 221 corresponding to both the imaging and non-imaging pixels 100, 100′ of the selected row.
The imager 200 may be partially or wholly formed upon an integrated circuit. For example, the pixel array 201, row circuitry 210, column circuitry 220, analog to digital converter 230, and digital processing circuit 240 may be incorporated into an integrated circuit. Portions of an integrated circuit, however, might be formed with defects. For example, when the column circuitry 220 is incorporated into an integrated circuit, some of the column circuits 221 may be defective, which may normally require rejecting that integrated circuit. Similarly, the row circuitry 210 may also include defects, which may also require rejecting the integrated circuit.
Additionally, as the photo and reset signals Vrst, Vsig are routed through the column circuitry 220, they are subject to noise. One type of noise is known as column fixed pattern noise (FPN). Column FPN is associated with the characteristics of the column circuit 221 that the reset and photo signals Vrst, Vsig travel through. Thus, even when each column circuit 221 is non-defective, some column circuits 221 may be associated with a higher level of column FPN than others.
Accordingly, there is a need and desire for an improved column circuitry architecture that is less susceptible to column FPN and which can tolerate defects. There is also a need and desire for an improved row circuitry architecture that can tolerate defects.